Fujitsu FR81S User Manual
CHAPTER 39: RAMECC
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAMECC
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
4.2. Double-bit ECC Error Address Register XBS RAM :
DEEARX
The bit configuration of double-bit ECC error address register XBS RAM is shown.
When the double-bit error detection is performed during the ECC check of XBS RAM, this register
maintains the address at which it occurred.
DEEARX : Address 2402
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
D14
D13
D12
D11
D10
D9
D8
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Attribute
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit15] Reserved.
Always write "0" to this bit.
[bit14 to bit0] D14 to D0 : Double-bit error occurrence address bits
When the double-bit error detection is performed during the ECC check, these bits maintain the address at
which it occurred.
If the event above is further detected when a value has already been set to these bits, the original value is
maintained without overwriting these bits.
Note:
The address above is offset in words. Calculate the absolute address by adding the lower 2 bits to the offset
address mentioned above, and then adding the base address of XBS RAM.
(Absolute address) = (0001_0000
H
) + (Offset indicated by DEEARX + 2b’00)
MB91520 Series
MN705-00010-1v0-E
1299