Fujitsu FR81S User Manual
CHAPTER 39: RAMECC
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAMECC
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
[bit15 to bit8] EY7 to EY0 : False error generation byte setting bits
EY7 to EY0
Target byte on RAM
EY0
RAM data[7:0]
EY1
RAM data[15:8]
EY2
RAM data[23:16]
EY3
RAM data[31:24]
EY4
RAM data[36:32]
EY5
RAM data[41:37]
EY6
RAM data[46:42]
EY7
RAM data[51:47]
These bits specify the byte position of the target that causes false ECC error (a pseudo ECC error) for
Backup-RAM.
For example, when EY2 is filled with "1" and other false error generation byte setting bits are filled with
"0", the target byte where a false error (a pseudo error) is generated is RAM data[23:16] only. In other bytes
on the RAM, no false error is generated.
In addition to the foregoing, when both EY2 and EY3 are filled with “1” and others are filled with “0”, the
target byte where a false error is generated is RAM data[31:16].
[bit7 to bit0] EI7 to EI0 : False error generation bit setting bits
EI7 to EI0
Target bit on byte
EI0
[0]
EI1
[1]
EI2
[2]
EI3
[3]
EI4
[4]
EI5
[5]
EI6
[6]
EI7
[7]
These bits specify bit position of the target that causes false ECC error (a pseudo ECC error). for
Backup-RAM.
For example, when both EY2 and EI4 are filled with “1”, and others are filled with “0”, the target bit where
a false error (a pseudo error) is generated is RAM data[20]. As a result, a single bit error can be corrected.
In addition to the foregoing, when EY2, EI4, and EI7 are filled with “1”, and others are filled with “0”, the
target bits where a false error (a pseudo error) is generated are RAM data[23] and RAM data[20]. As a
result, a double bit error can be detected.
Moreover, when EY2, EY3, and EI4 are filled with “1”, and others are filled with “0”, the target bits where
a false error (a pseudo error) is generated are RAM data[28] and RAM data[20]. As a result, a single bit
error can be corrected in each byte.
MB91520 Series
MN705-00010-1v0-E
1309