Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
4.1.5.
Transmission FIFO Interrupt Control Register:
FTICR
FTICR
Transmission FIFO interrupt control register (FTICR) is used to set the interrupt by the transmission
effective data count of the FIFO.
FTICRn(n=0 to 11): Address Base addr + 24
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
FTICR2[7:0]
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
FTICR1[7:0]
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15 to bit8] FTICR2: FIFO2 data count display bits
[bit7 to bit0] FTICR1: FIFO1 data count display bits
[bit7 to bit0] FTICR1: FIFO1 data count display bits
The FTICR register sets the interrupt trigger level by the effective data count of the transmission FIFO
(residual quantity). The table below shows the details of FCR1:FSEL bit settings.
FSEL
Transmission FIFO selection
Transmission FIFO interrupt control register
0
FIFO1
FTICR1
1
FIFO2
FTICR2
⋅
The initial values of the effective data count that generates the interrupt of the FTICR register are 0x00.
⋅
When the display of set number of data count and effective data count of transmission FIFO (FBYTE)
matches or becomes small, interrupt flag (FDRQ) is set to "1".
⋅
The effective data count to transmission FIFO is displayed.
FTICR2, FTICR1: FIFIO2 data count display bits, FIFO1 data count display bits
Write
The effective data count that generates the interrupt is set.
Read
The effective data count is read.
Notes:
⋅
The setting that exceeds the capacity of FIFO is prohibition.
⋅
The set value cannot be read.
⋅
This register cannot use the read-modify-write instruction.
MB91520 Series
MN705-00010-1v0-E
1342