Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
61
[bit4 to bit1] TDIV3-0: Timer operating clock division bits
These bits are used to set the division ratio of the serial timer.
TDIV3 TDIV2 TDIV1 TDIV0
Timer operating clock
Division
ratio
φ
=
8MHz
φ
=
10MHz
φ
=
16MHz
φ
=
20MHz
φ
=
24MHz
φ
=
32MHz
0
0
0
0
φ
125ns
100ns
62.5ns
50ns
41.67ns 31.25ns
0
0
0
1
φ
/2
250ns
200ns
125ns
100ns 83.33ns 62.5ns
0
0
1
0
φ
/4
500ns
400ns
250ns
200ns 166.67ns 125ns
0
0
1
1
φ
/8
1µs
800ns
500ns
400ns 333.33ns 250ns
0
1
0
0
φ
/16
2µs
1.6µs
1µs
800ns 666.67ns 500ns
0
1
0
1
φ
/32
4µs
3.2µs
2µs
1.6µs
1.33µs
1µs
0
1
1
0
φ
/64
8µs
6.4µs
4µs
3.2µs
2.67µs
2µs
0
1
1
1
φ
/128
16µs
12.8µs
8µs
6.4µs
5.33µs
4µs
1
0
0
0
φ
/256
32µs
25.6µs
16µs
12.8µs 10.67µs
8µs
φ
: Bus clock
Notes:
⋅
These bits can be changed only when the serial timer enable bit (TMRE) is set to "0".
⋅
Settings other than those listed above are prohibited.
[bit0] TMRE: Serial timer enable bit
This bit is used to enable or disable the operation of the serial timer.
TMRE
Serial timer enable bit
0
The operation of the serial timer will be stopped.
During stop, the value of the serial timer register (STMR)
will be retained.
1
If this bit is changed from "0" to"1", the value of the serial
timer register (STMR) will be initialized to "0", and the
operation of the serial timer will be started.
Notes:
⋅
When an external trigger is enabled (TRGE="1"), the serial timer will not start operation until an edge of
the external trigger set by the trigger select bits (SAGSR:TRG1, 0) is detected, even if this bit is set to
"1".
⋅
To perform synchronous transmission by the serial timer, or perform transmission by an external trigger,
change this bit under one of the following conditions:
⋅
Transmission disabled (SCR:TXE="0")
⋅
Transmission bus idle (SSR:TBI="1")
MB91520 Series
MN705-00010-1v0-E
1374