Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
67
4.3.9.
Serial Chip Select Timing Register: SCSTR3-0
The serial chip select timing register (SCSTR3-0) is used to set the setup delay time for serial chip select,
the hold delay time for serial chip select, and the deselect time for serial chip select.
SCSTR1n-0n(n=0 to 11) : Address Base addr + 12
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
CSSU7 CSSU6 CSSU5 CSSU4 CSSU3 CSSU2 CSSU1 CSSU0
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
CSHD7 CSHD6 CSHD5 CSHD4 CSHD3 CSHD2 CSHD1 CSHD0
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15 to bit8] CSSU7-0: Serial chip select setup delay bits
These bits are used to set a time interval between the timing when a serial chip select pin becomes active
and the timing half bit before a sampling point of the first data bit. If "00h" is set to these bits, the timing
half bit before a sampling point of the first data bit of the serial clock will be the same as the timing when a
serial chip select pin becomes active.
CSSU7 CSSU6 CSSU5 CSSU4 CSSU3 CSSU2 CSSU1 CSSU0 Setup delay time
0
0
0
0
0
0
0
0
No setup delay time
0
0
0
0
0
0
0
1
1×
Serial chip select timing
operating clock
0
0
0
0
0
0
1
0
2×
Serial chip select timing
operating clock
1
1
1
1
1
1
1
0
254×
Serial chip select timing
operating clock
1
1
1
1
1
1
1
1
255×
Serial chip select timing
operating clock
Notes:
⋅
These bits can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
⋅
In the slave mode (SCR:MS="1"), setting these bits has no effect.
⋅
If these bits are set to "00"h, the timing when a serial chip select pin becomes active will be the same as
the timing when the serial clock outputs an edge for the first time.
MB91520 Series
MN705-00010-1v0-E
1380