Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
100
4.4.11.
LIN Assist Mode Status Register: LAMSR
LIN assist mode status register (LAMSR) is used in order to check the status of automatic header
transmission/reception and to check whether there is any error flag received.
LAMSRn(n=0 to 11) : Address Base addr + 10
H
(Access: Byte, Half-word,
Word)
7
6
5
4
3
2
1
0
bit
LER
SER
RDRF
TDRE
TBI
LCSC
-
LAHC
0
0
0
1
1
0
0
0
Initial value
R,WX
R,WX
R,WX
R,WX
R,WX
R/W
R0,W0
R/W
Attribute
[bit7] LER: LIN representative error flag bit
When the following errors occur, this bit is set to "1". As for conditions on setting and clearing the error flag
bit, see the explanations for each bit of the LIN assist mode error status register (LAMESR).
⋅
LIN bus error flag bit (LBSER)
⋅
LIN Sync Data error flag bit (LSFER)
⋅
LIN ID parity error flag bit (LPTER)
⋅
LIN checksum error flag bit (LCSER)
LER
LIN representative error flag
0
No error
1
Error
Note:
In manual mode (LAMCR:LAMEN=0), the read value of this bit is always "0".
[bit6] SER: Serial interface representative error flag bit
When the following errors occur, this bit is set to "1".As for conditions on setting and clearing the error flag
bit, see the explanations for each bit of the serial status register (SSR); (SECTION: 4.4.2: Serial Status
Register).
⋅
framing error flag bit (FRE)
⋅
overrun error flag bit (ORE)
SER
Serial interface representative error flag
0
No error
1
Error
[bit5] RDRF: Reception data full flag bit
This bit is the mirror of the reception data full flag bit (RDRF) of the serial status register (SSR). As for the
explanation for this bit, see “SECTION: 4.4.2: Serial Status Register”.
[bit4] TDRE: Transmission data empty flag bit
This bit is the mirror of the transmission data empty flag bit (TDRE) of the serial status register (SSR). As
for the explanation for this bit, see “SECTION: 4.4.2: Serial Status Register”.
[bit3] TBI: Transmission bus idle flag bit
This bit is the mirror of the transmission bus idle flag bit (TBI) of the serial status register (SSR). As for the
explanation for this bit, see “SECTION: 4.4.2: Serial Status Register”.
MB91520 Series
MN705-00010-1v0-E
1413