Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
98
4.4.9.
Sync Field Lower Limit Register: SFLR
The Sync Field lower limit register (SFLR) is used to set the lower limit of the value which can be set to the
baud rate generator register for automatic baud rate adjustment.
SFLR1n-0n(n=0 to 11) : Address Base addr + 12
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
-
TL14
TL13
TL12
TL11
TL0
TL9
TL8
0
0
0
0
0
0
0
0
Initial value
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
TL7
TL6
TL5
TL4
TL3
TL2
TL1
TL0
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15] Undefined
The read value is "0". Writing has no effect on the operation.
[bit14 to bit0] TL14-0: Lower limit bits
These bits are used to set the lower limit of the value which can be set to the baud rate generator register
(BGR) for automatic baud rate adjustment.
When the automatic baud rate adjustment bit (SACSR:AUTE) is set to "1" and the slave mode is selected
(SCR:MS="1"), the value of the serial timer register (STMR) will be set to the baud rate generator register
(BGR), if the value of the serial timer register (STMR) after Sync Field is received is smaller than the Sync
Field upper limit register (SFUR) and larger than these bits.
Note:
These bits can be changed when the automatic baud rate adjustment bit (SACSR:AUTE) is set to "0".
MB91520 Series
MN705-00010-1v0-E
1411