Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
129
Write
- TDR1n-0n(n=3 to 8, 10, 11) : Address Base addr + 06
H
(Access: Byte,
Half-word, Word)
15
14
13
12
11
10
9
8
bit
-
-
-
-
-
-
-
-
-
Initial value
RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX
Attribute
7
6
5
4
3
2
1
0
bit
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
Initial value
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Attribute
The transmit data register (TDR) is the data buffer register for sending serial data.
⋅
Output to serial data line (SDA Pin) at the MSB first on transmit data register (TDR).
⋅
When you send the first byte, the least significant bit (TDR:D0) is the data direction bit.
⋅
Transmission data empty flag (SSR:TDRE) will be cleared to "0" when the transmission data is written
to the transmit data register (TDR).
⋅
Transmission data empty flag (SSR:TDRE) will be set to "1" when transferred to the transmit shift
register.
⋅
If transmission FIFO is disabled and the transmission data empty flag (SSR:TDRE) is "0", the
transmission data cannot be written to the transmit data register (TDR).
⋅
When using transmission FIFO, the transmission data can be written to the amount of transmission FIFO,
even if the transmission data empty flag (SSR:TDRE) is "0".
Notes:
Transmission data register is write-only register and receive data register is read-only register. Because the
two registers are located in the same address, write value and read value might be different. Therefore
instructions such as INC/DEC instructions which perform read-modify-write (RMW) operations cannot be
used.
MB91520 Series
MN705-00010-1v0-E
1442