Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
5. Operation of UART
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
144
Figure 5-2 Timing of Using FIFO
Timing to generate reception interrupt when reception FIFO is used
Reception data
FBYTE setting
(number of transfer)
RDRF
1
st
Byte
3
Generation of interrupt by the match of number of
FBYTE setting(number of transfer) and number of
reception data
Reading RDR
2
nd
Byte
3
rd
Byte
4
th
Byte
ST
SP
ST
SP ST
SP
ST
SP
ST
5
th
Byte
SP
Reading of
all reception data
0
1
2
3 2 1 0 1 2
FBYTE reading
(Valid byte display)
Timing to set ORE(overrun error) flag bit
Reception data
FBYTE setting (number of transfer)
RDRF
62
nd
Byte
62
(Notes)
An overrun error will occur if the next data is received when FBYTE reading indicates FIFO capacity.
The figure shows the case where 64-byte FIFO is user.
63
rd
Byte
64
th
Byte
65
th
Byte
ST
SP
ST
SP ST
SP
ST
SP
ST
66
th
Byte
SP
62 63 64
FBYTE reading(valid byte display)
ORE
Overrun error occurrence
MB91520 Series
MN705-00010-1v0-E
1457