Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
5. Operation of UART
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
157
5.2.8.
Parity Bit
⋅
Parity bit can be added only in operating mode 0. The parity enable bit (ESCR:PEN) can specify whether
to enable or disable the parity, and the parity selection bit (ESCR:P) can specify whether to use even
parity or odd parity.
⋅
Operation mode 1 does not use parity.
Figure 5-8 Operation with Parity Enabled
Reception
data(mode0)
Transmission
data(mode0)
Transmission
data(mode0)
ST D0
D1 D2
D4 D5 D6 D7
SP
SMR:PE
Occurrence of parity
error at reception using
even-parity (ESCR:
P=0)
D3
P
Transmission of even
parity (ESCR:P=0)
Transmission of odd
parity (ESCR:P=1)
ST:Start bit SP:Stop bit For 8-bit length including a parity (ESCR:PEN=1)
<
<
Note>The parity bit cannot be used for operating mode 1.
MB91520 Series
MN705-00010-1v0-E
1470