Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
184
Figure 6-2 Timing of Interrupts and Flag Setting
Timing to generate reception interrupt when reception FIFO is used
Reception data
FIFOBYTE
(reception)
(reception)
RDRF
1
st
Byte
3
Generation of interrupt by the match of
number of FBYTE settings ( number of transfer)
and number of reception data
number of FBYTE settings ( number of transfer)
and number of reception data
Reading RDR
2
nd
Byte
3
rd
Byte
4
th
Byte
5
th
Byte
Reading of all reception data
SCK
6
th
Byte
7
th
Byte
Valid byte display
0
1
2
3 2 1 0 1 2 3 2 1 0 1
Timing to set ORE (overrun error) flag bit
Reception data
FIFOBYTE
(reception)
(reception)
RDRF
1
st
Byte
60
Occurrence of interrupt by the match of
number of FIFOBYTE(reception) settings + 1
and number of reception data
number of FIFOBYTE(reception) settings + 1
and number of reception data
2
nd
Byte
3
rd
Byte
4
th
Byte
5
th
Byte
Overrun error occurrence
SCK
6
th
Byte
7
th
Byte
Valid byte display
59 60 61 62 63 64
ORE
(Notes)
An overrun error will occur if the next data is received when FIFO display indicates FIFO capacity.
The figure shows that 64-byte of FIFO capacity is used.
The figure shows that 64-byte of FIFO capacity is used.
MB91520 Series
MN705-00010-1v0-E
1497