Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
276
Overview of pseudo LIN Sync Data error test mode
The slave who checks Sync Field value (0x55) can execute the pseudo LIN Sync Data error test.
A pseudo LIN Sync Field error cannot be detected by the master who transmits Sync Field.
Figure 7-23 Overview of pseudo LIN Sync Field error test mode
SIN
SOUT
MPU(master side)
transceiver
Transmission
data
Reception data
(self-check)
LIN Sync Data error
No Generation object
transceiver
SIN
SOUT
MPU(slave side)
Reception data
LIN Sync Data error
Generation object
Reversing
output of data
of Sync Field
: Route for pseudo error
: Off the subject route for pseudo error
: Off the subject route for pseudo error
It is necessary to set the LIN Sync Data error pseudo trouble setting bit to effective (LAMERT:LSFERT=1)
by the method of starting the pseudo error test mode to start the pseudo LIN Sync Data error test mode. All
values (0x55) are reversed when the master who made the pseudo LIN Sync Data error pseudo trouble
setting effective (LAMERT:LSFERT=1) before the start bit of Sync Field transmits Sync Field and it
outputs it. It does continuing this operation until the pseudo LIN Sync Data error test mode setting is
released (LAMESR:LSFERT=0).
Notes
⋅
The detection of the LIN Sync Data error is detected in slave (SCR:MS=1) of assist mode
(LAMCR:LAMEN=1).
⋅
The header reception of the assist mode and the transmission/reception processing of the response stop
by LIN Sync Data error detection (LAMESR:LBSER=1).
Overview of pseudo LIN ID parity error test mode
The pseudo LIN ID parity error test can be executed by self-check of the master who transmits ID Field and
the slave who receives ID Field.
Figure 7-24 Overview of pseudo LIN ID parity error test mode
SIN
SOUT
MPU
(header/response transmission node)
transceiver
Transmission
data
Reception data
(self-check)
LIN ID parity error
generation
transceiver
SIN
SOUT
MPU
(header/response reception node)
Reception data
LIN ID parity error
generation
Reversing
output parity
bit of ID Field
It is necessary to set the LIN ID parity error pseudo trouble setting bit to effective (LAMERT:LPTERT=1)
by the method of starting the pseudo error test mode to start the pseudo LIN ID parity error test mode.
The master to whom the pseudo LIN ID parity error trouble setting was effectively set before the start bit of
ID Field (LAMERT:LPTERT=1) reverses all parity values (2bit) in ID Field when ID Field is transmitted
and outputs it.
The LIN ID parity error is generated when ID Field is received, and "1" is set by flag bit
(LAMESR:LPTER).
Field
Field
MB91520 Series
MN705-00010-1v0-E
1589