Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
277
Note:
The transmission/reception processing of the response of the assist mode stops by LIN ID parity error
detection (LAMESR:LPTER=1).
Overview of pseudo LIN checksum error test mode
The pseudo LIN checksum error test can be executed on the side where the self-check and the response on
the side where the response is transmitted are received.
Figure 7-25 Outline of pseudo LIN checksum error test mode
SIN
SOUT
MPU
(header/response transmission node)
transceiver
Transmission
data
Reception data
(self-check)
LIN checksum error
generation
transceiver
SIN
SOUT
MPU
(header/response reception node)
Reception data
LIN checksum error
generation
Reversing
output of
checksum data
It is necessary to set the LIN checksum error pseudo trouble setting bit to effective (LAMERT:LCSERT=1)
by the method of starting the pseudo error test mode to start the pseudo LIN checksum error test mode.
All the values are reversed when checksum is transmitted and the node to which the pseudo LIN checksum
error pseudo trouble was set before the start bit of checksum (LAMERT:LCSERT=1) is output.
The LIN checksum error occurs when checksum is received, and "1" is set by flag bit (LAMESR:LCSER).
The LIN checksum error is caused until the pseudo LIN checksum error test mode setting is released
(LAMESR:LCSERT=0).
MB91520 Series
MN705-00010-1v0-E
1590