Fujitsu FR81S User Manual
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
28
10.3.1.
MPU Control Register : MPUCR
The bit configuration of the MPU control register (MPUCR) is shown.
The MPU control register controls whether the MPU is enabled or disabled, and configures the access
permissions in privilege mode and user mode to default areas (areas not specified as protection areas).
MPUCR : Address 0312
H
(Access: Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PIE
PRE
PWE
UIE
URE
UWE
Reserved
BE
Initial value
0
0
0
0
0
0
-
0
Attribute R/W
R/W
R/W
R/W
R/W
R/W
R0,W0
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PAN[1:0]
DEE
MPE
Initial value
-
-
-
-
0
1
0
0
Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,WX R1,WX
R/W
R/W
[bit15] PIE (Privilege Mode Instruction Fetch Enable)
This bit is for permitting instruction fetch in privilege mode from the default areas (areas that have not been
specified as protection areas).
PIE
Access to default area
0
Instruction fetch not permitted in privilege mode (Initial value)
1
Instruction fetch permitted in privilege mode
[bit14] PRE (Privilege Mode Read Access Enable)
This bit is for permitting data read access in privilege mode from the default areas (areas that have not been
specified as protection areas).
PRE
Access to default area
0
Read access not permitted in privilege mode (Initial value)
1
Read access permitted in privilege mode
[bit13] PWE (Privilege Mode Write Access Enable)
This bit is for permitting data write access in privilege mode to the default areas (areas that have not been
specified as protection areas).
PWE
Access to default area
0
Write access not permitted in privilege mode (Initial value)
1
Write access permitted in privilege mode
MB91520 Series
MN705-00010-1v0-E
125