Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
336
8.3.3. Acknowledge Reception by Transmitting First Byte
When the data direction bit (R/W) is output, the I
2
C interface receives an acknowledge from the slave. The
operation varies depending on whether FIFO is enabled or disabled, as indicated in the following table:
Table 8-3 Operation after Acknowledge Reception (when DMA mode is disabled)
(IBSR:RSA = "0", SSR:DMA= "0")
Trans-
mission
FIFO
operatio
n
Recep-
tion
FIFO
operatio
n
Trans-
mission
FIFO
status
Recep-
tion
FIFO
status
Data
direction
bit
(R/W)
Operation immediately after acknowledge
reception
Acknowledge is ACK
Acknowledge
is NACK
Disabled Disabled
-
-
0
If the SSR:TDRE bit is "1", the IBCR:INT
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the IBCR:INT bit is
held to "0" and not waited.
The IBCR:INT
bit is set to "1"
and waited.
1
Disabled Enabled
-
Without
data
0
If the SSR:TDRE bit is "1", the IBCR:INT
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the IBCR:INT bit is
held to "0" and not waited.
The IBCR:INT
bit is set to "1"
and waited.
With
data
The IBCR:INT bit is set to "1" and waited.
-
1
If the SSR:TDRE bit is "1", the IBCR:INT
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the IBCR:INT bit is
held to "0" and not waited.
Enabled Disabled
-
-
0
If the SSR:TDRE bit is "1", the IBCR:INT
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the IBCR:INT bit is
held to "0" and not waited.
The IBCR:INT
bit is set to "1"
and waited.
1
Enabled Enabled
-
Without
data
0
If the SSR:TDRE bit is "1", the IBCR:INT
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the IBCR:INT bit is
held to "0" and not waited.
The IBCR:INT
bit is set to "1"
and waited.
With
data
The IBCR:INT bit is set to "1" and waited.
-
1
If the SSR:TDRE bit is "1", the IBCR:INT
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the IBCR:INT bit is
held to "0" and not waited.
MB91520 Series
MN705-00010-1v0-E
1649