Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
2.
F
EATURES
................................................................................................................................... 465
3.
C
ONFIGURATION
.......................................................................................................................... 466
4.
R
EGISTERS
................................................................................................................................. 467
4.1.
Interrupt Control Registers 00 to 47 : ICR00 to ICR47 (Interrupt Control Register 00 to
47): ............................................................................................................................... 468
5.
O
PERATION
................................................................................................................................. 469
5.1.
Setup .............................................................................................................................. 470
5.2.
Starting ........................................................................................................................... 471
5.3.
Determining Priorities .................................................................................................... 472
5.4.
Recovering From Stop Mode ......................................................................................... 473
5.5.
Recovering From Standby Mode (Power shutdown) ..................................................... 474
CHAPTER 13: EXTERNAL INTERRUPT INPUT ............................................................................... 475
1.
O
VERVIEW
.................................................................................................................................. 476
2.
F
EATURES
................................................................................................................................... 477
3.
C
ONFIGURATION
.......................................................................................................................... 478
4.
R
EGISTERS
................................................................................................................................. 479
4.1.
External Interrupt Factor Register 0/1 : EIRR0/EIRR1 (External Interrupt Request
Register 0/1) ................................................................................................................. 480
4.2.
External Interrupt Enable Register 0/1 : ENIR0/ENIR1 (ENable Interrupt request Register
0/1) ............................................................................................................................... 481
4.3.
External Interrupt Request Level Register 0/1 : ELVR0/ELVR1 (External interrupt LeVel
Register 0/1) ................................................................................................................. 482
5.
O
PERATION
................................................................................................................................. 483
6.
S
ETTING
...................................................................................................................................... 485
7.
Q&A ........................................................................................................................................... 486
8.
N
OTES
........................................................................................................................................ 487
CHAPTER 14: NMI INPUT.................................................................................................................. 489
1.
O
VERVIEW
.................................................................................................................................. 490
2.
F
EATURES
................................................................................................................................... 491
3.
C
ONFIGURATION
.......................................................................................................................... 492
4.
R
EGISTER
................................................................................................................................... 493
5.
O
PERATION
................................................................................................................................. 494
6.
U
SAGE
E
XAMPLE
......................................................................................................................... 495
CHAPTER 15: DELAY INTERRUPT .................................................................................................. 497
1.
O
VERVIEW
.................................................................................................................................. 498
2.
F
EATURES
................................................................................................................................... 499
3.
C
ONFIGURATION
.......................................................................................................................... 500
4.
R
EGISTERS
................................................................................................................................. 501
5.
O
PERATION
................................................................................................................................. 502
6.
R
ESTRICTIONS
............................................................................................................................ 503
CHAPTER 16: INTERRUPT REQUEST BATCH READ .................................................................... 505
1.
O
VERVIEW
.................................................................................................................................. 506
2.
F
EATURES
................................................................................................................................... 507
3.
C
ONFIGURATION
.......................................................................................................................... 508
4.
R
EGISTERS
................................................................................................................................. 509
4.1.
Interrupt Request Batch Read Register 0 upper-order : IRPR0H (Interrupt Request
Peripheral Read register 0H) ......................................................................................... 511
4.2.
Interrupt Request Batch Read Register 0 lower-order : IRPR0L (Interrupt Request
Peripheral Read register 0L) ........................................................................................ 512
4.3.
Interrupt Request Batch Read Register 1 upper-order : IRPR1H (Interrupt Request
Peripheral Read register 1H) ........................................................................................ 513
4.4.
Interrupt Request Batch Read Register 1 lower-order : IRPR1L (Interrupt Request
Peripheral Read register 1L) ........................................................................................ 514
4.5.
Interrupt Request Batch Read Register 3 upper-order : IRPR3H (Interrupt Request
Peripheral Read register 3H) ........................................................................................ 515
MB91520 Series
MN705-00010-1v0-E
(15)