Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
4.1. Overview
This section shows the overview of the registers.
The CAN includes the following registers:
⋅
CAN control register (CTRLR)
⋅
CAN status register (STATR)
⋅
CAN error counter (ERRCNT)
⋅
CAN bit timing register (BTR)
⋅
CAN interrupt register (INTR)
⋅
CAN test register (TESTR)
⋅
CAN prescaler extension register (BRPER)
⋅
IFx command request registers (IFxCREQ)
⋅
IFx command mask registers (IFxCMSK)
⋅
IFx mask registers 1, 2 (IFxMSK1, IFxMSK2)
⋅
IFx arbitration registers 1, 2 (IFxARB1, IFxARB2)
⋅
IFx message control register (IFxMCTR)(IFxMCTR)
⋅
IFx data registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
⋅
CAN transmission request registers 1, 2, 3, 4 (TREQR1,TREQR2,TREQR3,TREQR4)
⋅
CAN New Data registers 1, 2, 3, 4 (NEWDT1,NEWDT2,NEWDT3,NEWDT4)
⋅
CAN interrupt pending registers 1, 2, 3, 4 (INTPND1,INTPND2,INTPND3,INTPND4)
⋅
CAN message valid registers 1, 2, 3, 4 (MSGVAL1,MSGVAL2,MSGVAL3,MSGVAL4)
The CAN register is given an address space of 256 bytes (64 words) and accessible in byte or word mode.
The CPU accesses the message RAM via a message interface register.
MB91520 Series
MN705-00010-1v0-E
1700