Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
4.1.2. List of Overall Control Register
This section shows the list of overall control register.
Table 4-1 List of Overall Control Register
Address
Registers
Note
+0
+1
+2
+3
Base-addr + 00
H
CAN control register
(CTRLR)
CAN status register
(STATR)
STAR:
BOff, EWarn,
Epass = Read only
RxOk, TxOk, LEC
= Read/Write
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Reserved bits See the CTRLR. Reserved bits
See the STATR.
Reset: 00
H
Reset: 01
H
Reset: 00
H
Reset: 00
H
Base-addr + 04
H
CAN error counter
(ERRCNT)
CAN bit timing register (BTR)
ERRCNT: Read
only
BTR:
Write is enabled
when Init(CTLR)
= CCE(CTRLR) =
"1"
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
RP, REC[6:0]
TEC[7:0]
TSeg2[2:0],
TSeg1[3:0]
SJW[1:0],
BRP[5:0]
Reset: 00
H
Reset: 00
H
Reset: 23
H
Reset: 01
H
Base-addr + 08
H
CAN interrupt register
(INTR)
CAN test register
(TESTR)
INTR: Read only
TESTR:
Write is enabled
when
Test(CTRLR) =
"1"
"Rx" indicates the
level at the
CAN_RX pin.
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Int-Id[15:8]
Int-Id[7:0]
Reserved bits
See the TESTR.
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
&
0br0000000
Base-addr +
0C
H
CAN prescaler extension register
(BRPER)
Reserved bits
BRPER:
Write is enabled
when CCE(CTLR)
= "1"
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Reserved bits
BRPE[3:0]
-
-
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
MB91520 Series
MN705-00010-1v0-E
1702