Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
4.2.5. A/D Data Register : ADTCD0 to ADTCD47
The bit configuration of the A/D data register is shown.
The A/D data register (ADTCD) stores A/D conversion results.
ADTCD0 to ADTCD31: Address 138C
H
to 13CA
H
(Access: Byte, Half-word,
Word)
ADTCD32 to ADTCD47: Address 14F8
H
to 1516
H
(Access: Byte, Half-word,
Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ERR
ERRST
Reserved
D11
D10
D9
D8
Initial value
1
0
0
0
0
0
0
0
Attribute
R,WX
R,WX
R0,W0
R0,W0
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit7
D7
D6
D5
D4
D3
D2
D1
D7
Initial value
0
0
0
0
0
0
0
0
Attribute
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
[bit15] ERR : Conversion data error flag bit
ERR
Function
0
The conversion data is normal
1
The conversion data is not normal.
This bit indicates the presence of an error contained in the A/D conversion data. If this bit is “1”, the
value of the ERRST bit indicates the content of the error.
When this bit is read, it is set to “1”.
When new conversion result are writen in this register, this bit is cleard to “0”.
If the A/D data register protection function is enabled (ADTCS.PRT=1) and the activation factor is not
compare-match activation (ADTECS.STS2="0", ADTCS.STS1, STS0=11), this bit is read as “0”.
[bit14] ERRST : Conversion data error status bit (only when ERR = 1)
ERRST
Function
0
The conversion data is the old result.
1
The conversion data has overwritten the new data.
If the ERR bit is “1”, this flag indicates the content of the error in the A/D conversion data.
If the ERR bit is “1” and this bit is “0”, the conversion result read by the CPU are old data.
If the ERR bit and this bit are “1”, the previous conversion results have been overwritten by new
conversion results and are lost before they have not been completely read by CPU.
This bit is set to “1” if the previous conversion results have been overwritten by new conversion results
and lost before they have not been completly read by the CPU.
When this bit is read, it is cleared to “0”.
If the A/D data register protection function is enabled (ADTCS.PRT=1) and the conversion factor is not
compare-match activation (ADTECS.STS2="0", ADTCS.STS1, STS0=11), this bit is read as “0”.
MB91520 Series
MN705-00010-1v0-E
1838