Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
Note:
Please set the A/D data register protection clear select bit before operating the A/D conversion.
Please do not change the A/D data register protection clear select bit with the A/D conversion is requested
or the A/D data register protected.
[bit7,bit6] SEL1, SEL0 : Counting direction select bits
SEL1
SEL0
Function
0
0
Both counting up and down
0
1
Only counting up
1
0
Only counting down
1
1
Compare disabled
"If these bits are set to "00
B
", the compare-match operation is performed regardless of whether the
free-run timer is counting up or down.
"If these bits are set to "01
B
", the compare-match operation is performed only when the free-run timer is
counting up.
"If these bits are set to "10
B
", the compare-match operation is performed only when the free-run timer is
counting down.
"If these bits are set to "11
B
", the compare-match operation is not performed.
The compare-match operation is not performed while the selected free-run timer is inactive.
Note:
These bits must not be set to "10" when the 16-bit free-run timer is in the up count mode.
[bit5] BUFX : Compare register buffer function control bit
BUFX
Function
0
Enabled
1
disable
If this bit is set to "1", the buffer function is disabled.
If this bit is set to "0", the buffer function is enabled.
[bit4] BTS : Compare register buffer transfer control bit
BTS
Function
0
When 0 detection
1
When compare clear
If this bit is set to "0", the compare buffer register value will be transferred to the compare register when
0 is detected as the free-run timer value.
If this bit is set to "1", the compare buffer register value will be transferred to the compare register when
it matches the compare clear register of the free-run timer.
MB91520 Series
MN705-00010-1v0-E
1836