Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
50
4.2.12.
Scan Conversion Control Status Register :
ADSCANS0, ADSCANS1
The bit configuration of the scan conversion control status register is shown.
The scan conversion control status register (ADSCANS) selects continuousness and stop scan mode when
the conversion count is specified, selects scan conversion completion interrupt request enable/disable, and
indicates the state of the scan conversion completion interrupt request.
ADSCANS0: Address 1444
H
(Access: Byte, Half-word, Word)
ADSCANS1: Address 15B0
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCINT
SCIE
SCMD
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R(RM1),W
R/W
R/W
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
[bit7] SCINT : Scan conversion completion interrupt factor flag bit
SCINT
Explanation
Read
Write
0
Scan conversion completion interrupt factor clear
state when conversion count of each channel is
specified
Bit clear
1
State of interrupt factor generation by scan
conversion completion when conversion count of
each channel is specified
There is no change, and is no
influence on another.
The SCINT bit is set in "1" by the scan conversion completion when the conversion count of each
channel is specified.
When SCINT bit and scan conversion completion interrupt request enable bit are "1", the scan
conversion completion interrupt request when the conversion count is specified is generated.
Notes:
If the read-modify-write (RMW) instruction is executed, "1" will be read out.
The hardware set is given to priority when clear software (RCINT ="0" writing) and the hardware set are
generated at the same time.
[bit6] SCIE : Scan conversion completion interrupt request enable bit
SCIE
Explanation
0
Scan conversion completion interrupt disable
1
Scan conversion completion interrupt enable
When the scan conversion completion interrupt factor flag bit and the scan conversion completion interrupt
request enable bit are set in "1", the interrupt request is generated.
MB91520 Series
MN705-00010-1v0-E
1853