Fujitsu FR81S User Manual
CHAPTER 46: WORKFLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WORKFLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
5.1.1. Configuring CPU-ROM Mode below
Configuring CPU-ROM mode is shown below.
When the FWE bit of the WorkFlash control register (DFCTLR) is "0", it is CPU-ROM mode. When the
DFRDY bit of the WorkFlash status register (DFSTR) is "1", read from the flash memory is enabled in this
mode. In the mode, write to the flash memory is disabled. After released reset, the mode will be the
CPU-ROM mode.
MB91520 Series
MN705-00010-1v0-E
1986