Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
Operation of the dead time timer mode
The dead time generator inputs the compare output (OUT1, OUT3, OUT5) and outputs non-overlap signal
(inverted signal) to the external pins (RTO0 to RTO5).
Non-overlap signal generation by the normal polarity OUT1, OUT3, and
OUT5 (TMD8 to TMD0 of the 16-bit dead timer control registers (DTSCR0,
DTSCR1, DTSCR2) are 100
DTSCR1, DTSCR2) are 100
B
)
If you select the non-overlap signal of which DMOD2 to DMOD0 of the DTSCR0, DTSCR1, and DTSCR2
registers are "0" (normal polarity), the delay that corresponds to the non-overlap time configured at the 16-bit
dead timer registers (TMRR0 to TMRR2) will be applied. This delay will be applied to the rising edge or the
falling edge of the OUT1, OUT3, and OUT5 pins.
If the edge transition time of the OUT1, OUT3, and OUT5 is less than the non-overlap time configured, the
16-bit dead timer restarts counting down from the value of time from the dead timer start at the next RT edge
to the restart.
When the dead timer is activated once again before the counting down of the restarted dead timer ends, the
counting down will be restarted with the values of registers TMRR0 to TMRR2.
Figure 5-5 Non-overlap Signal Generation by the Normal Polarity Compare Output
TMRR0
setting value
Count value of
16-bit dead timer 0
Time
Compare output 1
RTO 0(U)
<Register setting>
RTO1(X)
2 peripheral clock cycles
Pin name
RTO0(U)
RTO2(V)
RTO4(W)
RTO1(X)
RTO3(Y)
RTO5(Z)
Output signal
Delayed signals are applied to the rising edge of compare output 1.
Delayed signals are applied to the rising edge of compare output 3.
Delayed signals are applied to the rising edge of compare output 5.
Delayed inverted signals are applied to the falling edge of compare output 1.
Delayed inverted signals are applied to the falling edge of compare output 3.
Delayed inverted signals are applied to the falling edge of compare output 5.
TCDT
:
"
XXXX
H
"
TCCS
:
"
X-XXXXXX X0X0XXXX ----XXXX
B
"
CPCLR
:
"
XXXX
H
"
(
cycle setting)
OCCP0 to OCCP5
:
"
XXXX
H
"
(
compare value)
OCS01 to OCS45
:
"
-XX1XXXX XXXXXX11
B
"
DTCR0 to DTCR2
:
"
0XXXX100
B
"
TMRR0 to TMRR2
:
"
XXXX
H
"
(
non-overlap timing setting)
DTMNS0
:
"
XX---000
B
"
SIGCR10
:
"
XXXXXX00
B
"
(
DTTI input and 16-bit dead timer count clock setting)
(Note) "X": Make a setting according to the operation.
MB91520 Series
MN705-00010-1v0-E
2081