Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
Operation in timer mode
If a rising edge of the OUT0 to OUT5 pins has been detected, the value will be reloaded to the 16-bit dead
timer and the timer starts counting down. The PPG timer continues to output to the RTO0 to RTO5 pins until
the 16-bit dead timer underflows.
PPG output pulse generation from the OUT rising edge through the 16-bit
dead timer underflow (TMD8 to TMD0 of the DTSCR0, DTSCR1, DTSCR2
registers are 010
registers are 010
B
)
Figure 5-4 Waveform Generated When the TMD2 to TMD0 are "010
B
"
TCDT
:
"
XXXX
H
"
TCCS
:
"
XXXXXXXX X0X0XXXX ----XXXX
B
"
CPCLR
:
"
XXXX
H
"
(
cycle setting)
OCCP0 to OCCP5
:
"
XXXX
H
"
(
compare value)
OCS01 to OCS45
:
"
-XX0XXXX XXXXXX11
B
"
DTCR0 to DTCR2
:
"
011XX010
B
"
TMRR0 to TMRR2
:
"
XXXX
H
"
(
non-overlap timing setting)
SIGCR10
:
"
XXXXXX00
B
"
(
DTTI input and 16-bit dead timer count clock setting)
PICS0
:
"
XX
H
"
(PPG0
output selection)
(Note) "X": Make a setting according to the operation.
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Count value
Time
Compare register 0
BFFF
H
Compare register 1
7FFF
H
Compare output 0
Compare output 1
GATE
Time of 16-bit
dead timer 0
PPG
Time of 16-bit
dead timer 0
RTO0
RTO1
<Register setting>
Note:
Each 16-bit dead timer will be used for two OUTs. In other words, the 16-bit dead timer 0 is used for OUT0
and OUT1, the 16-bit dead timer 1 is used for OUT2 and OUT3, and the 16-bit dead timer 2 is used for
OUT4 and OUT5. Thus, do not activate the timer which is already active, using the OUT. If you activate
such timer, the GATE signal output will be extended, which may cause a malfunction as a result.
MB91520 Series
MN705-00010-1v0-E
2080