Fujitsu FR81S User Manual
CHAPTER 49: BUS DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : BUS DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
4.1. Bus Diagnosis Status Register : BUSDIGSR
This section explains the bus diagnosis status register.
The bus diagnosis status register (BUSDIGSR) consists of a data parity error, address parity error, control
parity error, data direction, and error flag clear.
Bus diagnosis status register 0 indicates AHB error status. Bus diagnosis status register 1 indicates
APB(PCLK2) error status. Bus diagnosis status register 2 indicates Rbus(PCLK2) error status. Bus
diagnosis status register 3 indicates APB(PCLK1) error status. Bus diagnosis status register 4 indicates
Rbus(PCLK1) error status.
BUSDIGSR0: Address 3100
H
(Access: Half-word, Word)
BUSDIGSR1: Address 3102
H
(Access: Half-word, Word)
BUSDIGSR2: Address 3104
H
(Access: Half-word, Word)
BUSDIGSR3: Address 3116
H
(Access: Half-word, Word)
BUSDIGSR4: Address 3118
H
(Access: Half-word, Word)
15
14
13
12
11
10
9
8
BIT
DER[3]
DER[2]
DER[1]
DER[0]
AER[3]
AER[2]
AER[1]
AER[0]
0
0
0
0
0
0
0
0
Initial value
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
Attribute
7
6
5
4
3
2
1
0
BIT
PECLR
-
CNER
RDWR
0
0
0
0
0
0
0
0
Initial values
R0/W
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R,WX
R,WX
Attributes
[bit15 to bit12] DER3 to DER0: Data parity error
Data parity error flag. Parity is calculated for each piece of 8-bit data. If an error occurs, the associated bit is
set to "1".
For DER[3]=1, a parity error occurs in bit7 to bit0 of data.
For DER[2]=1, a parity error occurs in bit15 to bit8 of data.
For DER[1]=1, a parity error occurs in bit23 to bit16 of data.
For DER[0]=1, a parity error occurs in bit31 to bit24 of data.
If these bits are "0", this indicates that no error occurs. These bits are not updated while "1" is set in any one
of these bits. If these bits are set to "1", NMI occurs.
These bits are read-only. To clear them to "0", write "1" in the PECLR bit.
Notes:
⋅
These bits are not updated while any one of them is "1", any one of the AER bits is "1", or the CNER
bit is "1".
⋅
Data parity error detects an error for valid data of access size and notifies it.
⋅
Note that it may be led to infinite loop when an error is detected after the status register is read
immediately after an error of the bus diagnosis status register is cleared.
MB91520 Series
MN705-00010-1v0-E
2102