Fujitsu FR81S User Manual
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
4.1. TPU Unlock Register : TPUUNLOCK
The bit configuration of TPU unlock register is shown below.
TPUUNLOCK : Address 0900
H
(Access : Word)
bit31
bit0
UNLOCK[31:0]
Initial value
0000
0000
0000
0000
0000
0000
0000
0000
Attribute
R/W
This register is used to specify access prohibition/permission to the TPU control register (TPUCFG and
TPUTCN1n (n: timer channel number)).
It is required to prevent the illegal update of TPU control registers due to the malfunction of system.
Writing to this register is permitted only at the privileged mode. The readout value is always 0.
Access is limited in case of 32-bit width(word) because Lock/Unlock is judged with 32-bit.
[bit31 to bit0] UNLOCK[31:0] : LOCK/UNLOCK value
If present value of UNLCOK is written to the register, access to the TPU control register is permitted.
To prohibit accessing, write the values other than a present value of UNLCOK.
MB91520 Series
MN705-00010-1v0-E
2174