Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
37
4.17. SSCG Configuration Setting Register 1 : CCSSCCR1
(CCtl SSCg Config. Register 1)
The bit configuration of the SSCG configuration setting register 1 is shown.
Sets various settings of SSCG.
This register can be written only when PLL/SSCG clock oscillation stops. (CSELR.PCEN = "0").
CCSSCCR1: Address 052A
H
(Access : Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
RATESEL[2:0]
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R0,WX
R0,WX
R0,WX
R/W0
R/W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
[bit15 to bit13] RATESEL[2:0] (spread spectrum modulation RATE SELection) : spread spectrum
modulation rate selection
Sets the spread spectrum modulation rate of SSCG.
RATESEL[2:0]
Modulation rate
00x
0.5%
010
1%
011
2%
100
3%
101
4%
110
5%
111
Setting is prohibited
[bit12 to bit10] (Reserved)
Writing to these bits has no effect.
[bit9 to bit0] (Reserved)
Always write "0" to these bits.
MB91520 Series
MN705-00010-1v0-E
198