Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
4.18. Clock Gear Configuration Setting Register 0 :
CCCGRCR0 (CCtl Clock Gear Config. Register 0)
The bit configuration of the clock gear configuration setting register 0 is shown.
Sets various settings of clock gear.
CCCGRCR0: Address 052D
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
GRSTS[1:0]
Reserved
GRSTR
GREN
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX R(RM0),W1
R/W
[bit7, bit6] GRSTS[1:0] (clock GeaR STatuS flags) : Clock gear status flags
Displays status of Clock gear.
GRSTS[1:0]
Status
00
Stop in the state of clock gear low-speed oscillation or
No use of clock gear (CCCGRCR0.GREN=0) or
In the status of PLL/SSCG reset (CSELR.PCEN=0)
01
In operation of GEAR UP
10
Stop in the status of clock gear high-speed oscillation
11
In operation of GEAR DOWN
[bit5 to bit2] (Reserved)
[bit1] GRSTR (clock GeaR STaRt) : clock gear start
Writing "1" to this bit starts the operation of clock gear
The operation of clock gear depends on the value of the GRSTS bits. (Gear up or gear down)
When GRSTS=00
GRSTR
Operation
"0" write
Not affect the operation
"1" write
Start the operation of gear up
When GRSTS=01/11
GRSTR
OPeration
"0" write
Not affect the operation
"1" write
Not affect the operation
MB91520 Series
MN705-00010-1v0-E
199