Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
60
5.2.2. Selecting Stabilization Wait Time
Selecting the stabilization wait time is shown.
The stabilization wait time for each clock can be changed by setting of CSTBR and PLLCR .
Initial values after reset for clock oscillation stabilization wait time
⋅
Main clock
: CSTBR.MOSW[3:0] bit
2
15
× main clock period
⋅
PLL/SSCG clock
: PLLCR.POSW[3:0] bit
2
16
× main clock period
⋅
Sub clock
: CSTBR.SOSW[2:0] bit
2
8
× sub clock period
The main oscillation stabilization wait time is always specified by the initial value because
CSTBR.MOSW[3:0] is initialized by reset (INIT or RST). Except that case, the main oscillation stabilization
wait time can be changed by setting to CSTBR.MOSW[3:0].
The PLL/SSCG clock lock wait time is always specified by the initial value because PLLCR.POSW[3:0] is
initialized by reset (INIT or RST). Except that case, the PLL/SSCG clock lock wait time can be changed by
setting to PLLCR.POSW[3:0]. Set "1" to CSELR.PCEN after setting to PLLCR.POSW[3:0]. For details, see
the explanation of POSW in "4.8 PLL Setting Register : PLLCR (PLL Configuration Register)".
The sub oscillation stabilization wait time is always specified by the initial value because
CSTBR.SOSW[2:0] is initialized by reset (INIT or RST). Except that case, the sub oscillation stabilization
wait time can be changed by setting to CSTBR.SOSW[2:0].
MB91520 Series
MN705-00010-1v0-E
221