Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4.3.
Wild Register Data Register 00 to 15 : WRDR00 to 15 (Wild Register Data Register 00 to
15) ............................................................................................................................... 1171
5.
O
PERATION
................................................................................................................................ 1172
6.
U
SAGE
E
XAMPLE
........................................................................................................................ 1173
CHAPTER 34: CLOCK SUPERVISOR ............................................................................................ 1175
1.
O
VERVIEW
................................................................................................................................. 1176
2.
C
ONFIGURATION
......................................................................................................................... 1177
3.
R
EGISTER
.................................................................................................................................. 1178
3.1.
Clock Supervisor Control Register : CSVCR(Clock SuperVisor Control Register) .......... 1179
4.
O
PERATION
................................................................................................................................ 1182
4.1.
Initial State ........................................................................................................................ 1183
4.2.
Stopping CR Oscillator and the Clock Supervisor Function ............................................. 1184
4.3.
Re-enabling the Clock Supervisor .................................................................................... 1185
4.4.
Sub Clock Mode ............................................................................................................... 1186
4.5.
Stop Mode ........................................................................................................................ 1187
4.6.
Watch Mode ..................................................................................................................... 1188
4.7.
Checking the Reset Factor Using the Clock Supervisor .................................................. 1189
4.8.
Return from CR Clock ...................................................................................................... 1190
4.9.
Sub Clock Mode Enabled by Setting SCKS Bit ................................................................ 1191
CHAPTER 35: REGULATOR CONTROL......................................................................................... 1193
1.
O
VERVIEW
................................................................................................................................. 1194
2.
F
EATURES
.................................................................................................................................. 1195
3.
C
ONFIGURATION
......................................................................................................................... 1196
4.
R
EGISTER
.................................................................................................................................. 1197
4.1.
Regulator Output Voltage Select Register : REGSEL (REGulator output voltage SELect
register) ....................................................................................................................... 1198
5.
O
PERATION
............................................................................................................................... 1200
CHAPTER 36: EXTERNAL BUS INTERFACE ................................................................................ 1201
1.
O
VERVIEW
................................................................................................................................ 1202
2.
F
EATURES
................................................................................................................................. 1203
3.
C
ONFIGURATION
........................................................................................................................ 1204
4.
R
EGISTERS
............................................................................................................................... 1205
4.1.
CS Area Setting Registers: ASR0 to ASR3 (Area Setting Register 0-3) ......................... 1206
4.2.
CS Bus Setting Registers: ACR0 to ACR3 (Area Configuration Register 0-3) ............... 1209
4.3.
CS Wait Registers : AWR0 to AWR3 (Area Wait Register 0-3) ........................................ 1211
4.4.
External DMA Transfer Registers: DMAR0-3 (DMA transfer Register 0-3) ..................... 1216
5.
O
PERATION
............................................................................................................................... 1218
5.1.
External Pin Table ............................................................................................................ 1219
5.2.
External Bus Signal Protocol ........................................................................................... 1221
5.2.1.
Address/Data Split Bus Read Protocol ............................................................................................... 1221
5.2.2.
Address/Data split bus write protocol ................................................................................................. 1223
5.2.3.
Address/Data multiplexed bus read protocol ..................................................................................... 1224
5.2.4.
Address/Data multiplexed bus write protocol .................................................................................... 1226
5.3.
Address Alignment .......................................................................................................... 1228
5.4.
Split Access ..................................................................................................................... 1229
5.5.
Data Alignment ................................................................................................................ 1230
5.6.
Address Information ........................................................................................................ 1233
5.6.1.
Address information and output pins .................................................................................................. 1233
5.6.2.
Address type .......................................................................................................................................... 1233
5.7.
Idle Cycle Insertion Function ........................................................................................... 1234
5.8.
External Bus Output Signal Timing Settings ................................................................... 1235
5.9.
RDY Pin Access Cycle Extension Function..................................................................... 1240
5.10.
CS Setting Flow ........................................................................................................... 1241
5.11.
Example of Connecting to Asynchronous Memory ...................................................... 1249
5.12.
Example of Connection to Little Endian Device ........................................................... 1250
MB91520 Series
MN705-00010-1v0-E
(25)