Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
CHAPTER 37: BUS PERFORMANCE COUNTERS ........................................................................ 1251
1.
O
VERVIEW
................................................................................................................................ 1252
2.
F
EATURES
................................................................................................................................. 1253
3.
C
ONFIGURATION
........................................................................................................................ 1254
4.
R
EGISTERS
............................................................................................................................... 1255
4.1.
BPC-A Control Register : BPCCRA (Bus Performance Counter Control Register A) ..... 1256
4.2.
BPC-B Control Register : BPCCRB (Bus Performance Counter Control Register B) .... 1258
4.3.
BPC-C Control Register : BPCCRC (Bus Performance Counter Control Register C) .... 1259
4.4.
BPC-A Count Register : BPCTRA (Bus Performance CounTer Register A) ................... 1260
4.5.
BPC-B Count Register : BPCTRB (Bus Performance CounTer Register B) ................... 1261
4.6.
BPC-C Count Register : BPCTRC (Bus Performance CounTer Register C) .................. 1262
5.
O
PERATION
............................................................................................................................... 1263
5.1.
Setting ............................................................................................................................. 1264
5.2.
Starting and Stopping ...................................................................................................... 1266
5.3.
Operation ......................................................................................................................... 1267
5.4.
Measurement and Result Processing ............................................................................. 1268
CHAPTER 38: CRC .......................................................................................................................... 1271
1.
O
VERVIEW
................................................................................................................................ 1272
2.
F
EATURES
................................................................................................................................. 1273
3.
C
ONFIGURATION
........................................................................................................................ 1274
4.
R
EGISTERS
............................................................................................................................... 1275
4.1.
CRC Control Register : CRCCR (CRC Control Register) ........................................... 1276
4.2.
CRC Initial Value Register : CRCINIT (CRC Initial value register) .................................. 1277
4.3.
CRC Input Data Register : CRCIN (CRC INput data register) ........................................ 1278
4.4.
CRC Register : CRCR (CRC Register) ........................................................................... 1279
5.
O
PERATION
............................................................................................................................... 1280
5.1.
CRC Definition ................................................................................................................. 1281
5.2.
Reset Operation .............................................................................................................. 1282
5.3.
Initialization ...................................................................................................................... 1283
5.4.
Byte and Bit Orders ......................................................................................................... 1284
5.5.
CRC Calculation Sequence ............................................................................................. 1285
5.6.
Examples ......................................................................................................................... 1286
5.6.1.
Example 1 CRC16, Fixed Byte Input .................................................................................................. 1287
5.6.2.
Example 2 CRC16, Mixture of Different Input Bit Widths ................................................................. 1289
5.6.3.
Example 3 CRC32, Byte Order, Big-endian ....................................................................................... 1290
5.6.4.
Example 4 CRC32, Byte Order, Little-endian .................................................................................... 1291
CHAPTER 39: RAMECC .................................................................................................................. 1293
1.
O
VERVIEW
................................................................................................................................ 1294
2.
F
EATURES
................................................................................................................................. 1295
3.
C
ONFIGURATION
........................................................................................................................ 1296
4.
R
EGISTERS
............................................................................................................................... 1297
4.1.
Single-bit ECC Error Address Register XBS RAM : SEEARX ........................................ 1298
4.2.
Double-bit ECC Error Address Register XBS RAM : DEEARX ....................................... 1299
4.3.
ECC Error Control Register XBS RAM : EECSRX .......................................................... 1300
4.4.
ECC False Error Generation Address Register XBS RAM : EFEARX ............................ 1301
4.5.
ECC False Error Generation Control Register XBS RAM : EFECRX ............................. 1302
4.6.
Single-bit ECC Error Address Register BACKUP-RAM : SEEARA ................................ 1304
4.7.
Double-bit ECC Error Address Register BACKUP-RAM : DEEARA ............................... 1305
4.8.
ECC Error Control Register BACKUP-RAM : EECSRA .................................................. 1306
4.9.
ECC False Error Generation Address Register BACKUP-RAM : EFEARA .................... 1307
4.10.
ECC False Error Generation Control Register BACKUP-RAM : EFECRA.................. 1308
5.
O
PERATION
............................................................................................................................... 1310
5.1.
RAMECC Function ........................................................................................................... 1311
5.2.
Interrupt-related Register ................................................................................................ 1312
5.3.
Test Mode ........................................................................................................................ 1313
5.4.
Note ................................................................................................................................. 1314
MB91520 Series
MN705-00010-1v0-E
(26)