Fujitsu FR81S User Manual
CHAPTER 7: RESET
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.3. CPU Abnormal Operation Register : CPUAR (CPU
Abnormal operation Register)
The bit configuration of the CPU abnormal operation register is shown.
This register indicates the status and settings associated with the abnormal operation of CPU.
CPUAR : Address 051A
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PSTRE
Reserved
PMDF
PSTF
HWDF
Initial value
0
0
0
0
*
*
*
*
Attribute
R/W
R0,WX R0,WX
R0,WX RX,WX R(RM1),W R(RM1),W R(RM1),
W
* : It will be initialized to "0" by RSTX pin asserts (including simultaneous assert with NMIX). It will not be
initialized by the other reset factors.
[bit7] PSTRE (illegal PLL-run to STandby Reset Enable) : Illegal standby mode transition detection
reset enable
This bit configures whether or not to issue a reset when a watch mode or a stop mode transition has been
detected (illegal standby mode transition) with the PLL clock selected as a clock source.
When enabled, a reset due to the illegal standby mode transition detection factor will be generated at a
transition from the PLL-run state to watch mode or stop mode.
PSTRE
Description
0
Reset will not be generated (initial value)
1
Reset generation enabled
Note:
When you set this bit, make sure to clear the PSTF bit by writing "0" to the PSTF bit before setting this bit. If
you set this bit before clearing the PSTF bit, a reset may be generated since the value of the PSTF bit after the
power-on reset is indefinite.
[bit2] PMDF (PLL mode Main clock Down detection Flag) : PLL mode main oscillation determination
detection flag
When the clock supervisor does the main oscillation determination detection when PLL output is selected as a
clock source, this bit is set. Moreover, the source clock is written automatically in main mode (CKS=
CKM=00), and reset (RST level) is generated at once.
If a read-modify-write instruction is executed, "1" will be read out.
PMDF
Read
Write
0
The main oscillation determination detection is not in PLL
mode. (initial value)
Clear this bit
1
The main oscillation determination detection is in PLL mode.
No effect
MB91520 Series
MN705-00010-1v0-E
264