Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
[bit31] DME (DMA Enable) : DMA operation enabled
This bit controls the operation of the entire DMAC. When this bit is "0", a DMA transfer will not be
performed even if operation of each channel is enabled. When this bit is "1", operations according to the
settings for each channel are performed.
If "0" is written while a DMA transfer is in progress, the transfer is stopped in blocks specified in
DCCRn:BLK.
DME
DMA operation enable
0
DMA operation disabled (Initial value)
1
DMA operation enabled
[bit30 to bit16] Reserved
Always write "0" to these bits. The read value is "0".
[bit15] AT (Arbitration Type) : Priority setting
This bit configures how to determine priority for each channel. If the priority is set to "fixed" (AT = 0),
ascending order, ch.0 > ch.1 > ch.2 > ch.3, is taken. If the priority is set to "round robin" (AT = 1), DMAC
makes the priority of the channel which started the transfer the lowest and raises the priority of following
channels one by one. The decision on priority is made on each transfer of a block unit specified in
DCCRn:BLK regardless of the priority setting.
AT
Priority setting
0
Fixed (initial value)
1
Round robin
[bit14 to bit0] Reserved
Always write "0" to these bits. The read value is "0".
MB91520 Series
MN705-00010-1v0-E
309