Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
4.8. DMA Transfer Suppression Level Register : DILVR
(DMA-halt by Interrupt Level Register)
This section explains the bit configuration for DMA transfer suppression level register.
This register is 8-bit register to control the DMA transfer suppression by peripheral interrupts. This register
must be accessed as a 8-bit data.
DILVR: Address 0DF7
H
(Access: Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
LVL4
LVL[3:0]
Initial value
0
0
0
1
1
1
1
1
Attribute R0,W0 R0,W0 R0,W0 R1,WX
R/W
R/W
R/W
R/W
[bit7 to bit5] Reserved
Always write "0" to these bits. The read value is "0".
[bit4 to bit0] LVL (Level) : DMA suppression interrupt level
These bits set an interrupt level for suppression of DMA transfer. If a peripheral interrupt having an
interrupt level higher than the one specified by this register occurs, the DMA transfer is suppressed. LVL4
is fixed to "1", but LVL[3:0] can be set to any level.
LVL[4:0]
DMA suppression control
11111
Suppresses the DMA transfer when any peripheral interrupt request is issued.
(initial value)
11110
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1E
H
is issued.
11101
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1D
H
is issued.
11100
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1C
H
is issued.
11011
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1B
H
is issued.
11010
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 1A
H
is issued.
11001
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 19
H
is issued.
11000
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 18
H
is issued.
10111
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 17
H
is issued.
10110
Suppresses the DMA transfer when a peripheral interrupt request having a level
higher than 16
H
is issued.
MB91520 Series
MN705-00010-1v0-E
322