Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.1. DMA Request Clear Register 0 : ICSEL0 (Interrupt
Clear SELect register 0)
The bit configuration of DMA request clear register 0 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #16).
ICSEL0 : Address 0400
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
EISEL[2:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
R/W
R/W
[bit2 to bit0] EISEL[2:0] (External Interrupt request SELection) : Interrupt clear selection bits for
external interrupts 0 to 7
EISEL[2:0]
Clear target
000
External interrupt 0
001
External interrupt 1
010
External interrupt 2
011
External interrupt 3
100
External interrupt 4
101
External interrupt 5
110
External interrupt 6
111
External interrupt 7
MB91520 Series
MN705-00010-1v0-E
355