Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.3. DMA Request Clear Register 2 : ICSEL2 (Interrupt
Clear SELect register 2)
The bit configuration of DMA request clear register 2 is shown below.
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt
vector number #18).
ICSEL2: Address 0402
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
RTSEL0
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
[bit0] RTSEL0 (Reload Timer SELection) : Interrupt clear selection bit for reload timer 0/1
RTSEL0
Clear target
0
Reload timer 0
1
Reload timer 1
MB91520 Series
MN705-00010-1v0-E
357