Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
24
4.15. DMA Request Clear Register 16 : ICSEL16 (Interrupt
Clear SELect register 16)
The bit configuration of DMA request clear register 16 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #55).
ICSEL16: Address 0410
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
ICUSEL3[3:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R,W
R,W
R,W
R/W
[bit3 to bit0] ICUSEL3[3:0] : Interrupt clear selection for ICU ch.9
ICUSEL3[3:0]
Clear target
0000
Reserved (Does not clear any)
0001
32-bit ICU ch.9
0010
WG dead timer underflow 0
0011
WG dead timer underflow 1
0100
WG dead timer underflow 2
0101
WG dead timer reload 0
0110
WG dead timer reload 1
0111
WG dead timer reload 2
1000
WD DTTI0
1001 to 1111
Any clearness is not selected
Note:
Setting ICUSEL3[3:0]= "00000" is prohibited. During this setting, no interrupt clear will be selected.
MB91520 Series
MN705-00010-1v0-E
369