Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
41
5.2. Notes
The notes is shown.
⋅
Do not change the IORR and ICSEL registers when the DMAC enables DMA transfer requests issued
by peripherals.
⋅
Peripherals to which resource numbers (RN) are not assigned (see "APPENDIX") cannot use the
feature for clearing interrupts after the completion of DMA transfer. It should therefore be noted that
once such a peripheral has requested DMA transfer, the interrupt will not be cleared after the
completion of the requested DMA transfer.
⋅
Interrupt requests used as transfer requests are considered as interrupt requests addressed to the CPU.
Therefore, configure the interrupt controller to disable interrupts. (ICR register)
MB91520 Series
MN705-00010-1v0-E
386