Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
40
5.1. Configuration
The configuration of the operation is shown.
The operating sequence is as follows:
1. On the IORR, set the interrupt vector number of the transfer request source peripheral and the IOE bit.
2. Set ICSEL if multiple peripherals is assigned to the vector number selected in step 1.
3. Set the interrupt configuration-related registers for the peripheral.
4. Configure the DMAC.
MB91520 Series
MN705-00010-1v0-E
385