Fujitsu FR81S User Manual
CHAPTER 11: I/O PORTS
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
48
5.1. Pin I/O Assignment
The pin I/O assignment is shown below.
Pin I/O assignment is explained here. The I/O direction of each pin is controlled based on the configuration
shown below.
Figure 5-1 Configuration of Pin I/O Directions, Output Value Selection, and Input Value
Retrieval
As explained in the pertinent section concerning pin assignment, first change the PFR setting to enable the
port function. Since the pin then functions as a port, also set the DDR and PDR values in advance if
necessary. When doing this, note that the I/O direction of the pin is once set as specified by the DDR. For a
pin with the AD converter function, set the applicable bit in the analog input enable register (ADER) of the
AD converter to "Port I/O mode". For information on the setting method, see "CHAPTER: A/D
CONVERTER".
Refer PDR read value at 4.1. "
7BPort Data Register 00 to 19 : PDR00 to 19 (Port Data
Register 00 to 19)
"
PFR
EPFR
PDR
Pin
DDR
EPFR
PDDR
Peripheral
output value
External bus
Output value
Peripheral I/O
direction control
To peripheral
input value
External bus I/O
direction control
To input I/O relocation selection circuit
Input I/O relocation selection circuit
To external bus input value
Input value from each pins
To peripheral input value
MB91520 Series
MN705-00010-1v0-E
443