Fujitsu FR81S User Manual
CHAPTER 11: I/O PORTS
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
64
5.8. Key Code Register Function Settings
Setting when using the Key Code Register is shown.
The following settings are necessary for the key code register (KEYCDR) in order to write to the key code
target register.
• Set KEY1+KEY0+Access Size (SIZE)+Access address (RADR[12:0]) to the key code register using
half-word.
• Write (KEY1,KEY0) continuously according to the order (0,0), (0,1), (1,0), and (1,1). Set the address and
access size to the same value four times when (KEY1,KEY0) is written four times.
The following is a flow chart.
Figure 5-8 Key code flow chart
KEYCDR
KEY[1:0]
SIZE
RADR[12:0]
Written value
00
Access size
Access address lower 13 bits
KEYCDR
KEY[1:0]
SIZE
RADR[12:0]
Written value
01
Access size
Access address lower 13 bits
KEYCDR
KEY[1:0]
SIZE
RADR[12:0]
Written value
10
Access size
Access address lower 13 bits
KEYCDR
KEY[1:0]
SIZE
RADR[12:0]
Written value
11
Access size
Access address lower 13 bits
Write to address set by RADA (lower 13 bits match ) with the access size set by SIZE
If the following conditions apply, the key code will not be released and writing will not be executed to the
target register. In this case, it is necessary to set the key code register again from the beginning.
• When writing order for (KEY1,KEY0) is different
• When the data written to the SIZE bit is changed in the middle
• When the data written to the RADR bit is changed in the middle
• When the access size written to the SIZE bit is different from the size when accessing the actual target
register
• When the address (lower 13 bits) written to the RADR bit is different from the address (lower 13 bits)
when accessing the actual target register
• When the key code register and register related to the port are read while writing to the key code
register
Notes:
⋅
The key code setting might be canceled by DMA transfer. Read the value written in the object register,
and confirm whether the value has been changed.
⋅
While debugging by the on-chip debugger (OCD), the key code setting is canceled when the break
function is executed during the key code setting.
⋅
The DDR, PFR, EPFR, PPER, PILR, PODR, ADER, and DAER are the target key code registers. It is
necessary to set the key code in order to execute writing.
Start
End
MB91520 Series
MN705-00010-1v0-E
459