Fujitsu FR81S User Manual
MB91520 Series
FUJITSU SEMICONDUCTOR LIMITED
FUJITSU SEMICONDUCTOR CONFIDENTIAL
iii
How to Use This Manual
Finding a function
The following methods can be used to search for the explanation of a desired function in this manual:
⋅
Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
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Search from the register
The register list for this device has been described. You can look up the name of a desired register on the
list to find the address of its location or the page that explains it.
The address where each register is located is not described in the text. To verify the address of a register,
see "B. I/O Map" of "APPENDIX".
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Search from the index
You can look up the keyword such as the name of a peripheral function in the index to find the
explanation of the function.
About the chapters
Basically, this manual explains 1 peripheral function per chapter.
Terminology
This manual uses the following terminology.
Term
Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
How to Read This Manual
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Primary Terms
The following explains the primary terms used in this series
Term
Explanation
XBS
A 32-bit width, high-speed internal bus.
The bus master is used for access from the CPU (for instruction fetch), the CPU (for
data reading or writing), or the on-chip bus.
The bus slave is used to access to the on-chip bus, RAM (via the XBS built-in wild
register), and flash memory.
The bus has a crossbar switch configuration, and a circuit from each bus master to
each bus slave can operate simultaneously.
On-chip bus
A 32-bit width, high-speed internal bus. It has a 2-layer structure for XBS and DMA, and they
can operate simultaneously.
The bus master of the XBS layer is accessed from the XBS.
The bus master of the DMA layer is accessed from the DMA.
The bus slave of both layers has an external bus interface, CAN, 16/32-bit peripheral bus
bridge and others.
The bus slave of only DMA layer has an access to the XBS.
can operate simultaneously.
The bus master of the XBS layer is accessed from the XBS.
The bus master of the DMA layer is accessed from the DMA.
The bus slave of both layers has an external bus interface, CAN, 16/32-bit peripheral bus
bridge and others.
The bus slave of only DMA layer has an access to the XBS.
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