Fujitsu FR81S User Manual
CHAPTER 17: PPG
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
Interrupt factors
⋅
One of the following six interrupts is selected:
⋅
Software trigger or external trigger (TRG pin)
⋅
Borrow occurrence on the counter (match with the specified cycle)
⋅
Duty match
⋅
Borrow occurrence on the counter (match with the specified cycle) or duty match
⋅
Timing Point Capture match
⋅
Empty flag of PPG communication data register
Activation triggers
⋅
Software trigger (set with software trigger bit)
⋅
External trigger (TRG pin)
The activation trigger is input from an external.
The activation trigger is selected from one of the following triggers:
⋅
Internal trigger (EN0 to EN47)
⋅
External trigger (TRG pins 0 to 11)
⋅
Reload timer 0/1
GATE function
⋅
PPG is activated/stopped by GATE signals from the waveform generator.
Start Delay Mode
⋅
Support for PWM, One-shot operation, Normal Wave Form, and Center Aligned Wave Form.
⋅
Setting range = 0 to 65535 (specified by a 16-bit register)
⋅
Delay range = Count Clock × (PSDR Resister value + 1)
(Example) Normal Wave Form: Count Clock = 32MHz (31.25ns), PSDR=63999
Cycle = 31.25ns × (63999 + 1) = 2ms
(Example) Center Aligned Wave Form = Count Clock = 32MHz (31.25ns), PSDR=63999
Cycle = 31.25ns × {(63999 + 1) × 2} = 4ms
Timing Point Capture Mode
⋅
The AD activation trigger is generated according to the timing of the Timing Point Capture setting value.
PPG communication Mode
⋅
Cycle of High format and Low format, and setting of duty.
MB91520 Series
MN705-00010-1v0-E
548