Fujitsu FR81S User Manual
CHAPTER 17: PPG
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
3. Configuration
This section explains the configuration of the PPG.
Figure 3-1 Configuration Diagram of PPG
MDSE
PCN: bit13
0
PWM operation
1
One-shot operation
OWFS
PCN: bit8
0
Normal Wave Form
1
Center Aligned Wave Form
Cycle Value
PCSR
Duty Value
PDUT
Buffer
Buffer
Compa
rison
Output
level(latch)
Control
Circuit
Prescaler
CKS1, CKS0 PCN: bit11. bit10
0
EXT_CNTEN
1
EXT_CNTEN/4
0
0
0
EXT_CNTEN/16
1
1
EXT_CNTEN/64
1
CNTE
PTRG: bit15
0
Stop
1
Enable operation
RTRG
PTRG: bit12
0
Disable restart
1
Enable restart
IRQF
PCN: bit14
0
No interrupt request
1
Interrupu request
0 write: Clearing IRQF
IREN
PCN: bit5
0
Disable interrupt
1
Enable interrupt
PCN: bit9. bit0
OSEL
PGMS
Normal output
0
0
Inverted output
1
0
Clamp “L”output
0
1
Clamp “H”output
1
1
IRQ
PCN: bit3. bit2
IRS0
IRS1
STGR=0
Input of software trigger or external trigger
STGR=1
Input of GATE signal trigger
0
0
Counter borrow occurrence
1
0
Duty value match
0
1
Counter borrow ocurrence or duty value match
1
1
STRG
PTRG: bit14
0
No effect on operation
1
Software trigger
Edge
selection
EGS1, EGS0
PCN: bit7. bit6
0
No effect on operation
1
Rising edge
0
0
0
Falling edge
1
1
Both edge
1
EXT_CNTEN
Level
detection
EDGE
GATEC: bit0
0
Rising activation → falling stop
1
Falling activation → rising stop
STGR
GATEC: bit1
0
Activation by activation
trigger
1
Activation by activation
signal from waveform
generator
TRG
GATE
PSTR
Compa
rison
Timing Point Capture
Setting Value (PTPC)
PTMR
ADTRG
Reload
Reload
Reload
PPG
Start Delay Setting Value
(PSDR)
STRD
PCN2: bit8
0
Start Delay disable
1
Start Delay enable
TPC
PCN2: bit9
0
Timing Point Capturedisable
1
Timing Point Captureenable
CMD
PCN2: bit10
0
PPG communication mode disable
1
PPG communication mode enable
SREMP
PCN2: bit1
0
1
PPG communication data shift register Empty flag
(NotEmpty state)
PPG communication data shift register Empty flag
(Empty state)
REMP
PCN2: bit2
0
1
PPG communication data register Empty flag
(NotEmpty state)
PPG communication data register Empty flag
(Empty state)
CMDSEL
PCN2: bit11
0
Data LSB output
1
data MSB output
HFPR/LFPR
PCN: bit13,12
0
Low Pulse output
1
High Pulse output
Pulse Select
High/Low format
Cycle Value
PHCSR/PLCSR
High/Low format Duty
Value
PHDUT/PLDUT
PPG communication mode data setting value
(PCMDDT)
PPG communication mode data bit length setting value
PPG communication mode data bit length setting value
(PCMDWD)
IRS2
0
0
0
0
Timing Point Capture value match
1
PPGcommunication data register Empty factor
上記以外
0
0
Buffer
Buffer
GTREN0:bit0
GTREN0:bit1
GTREN0:bit1
EN0
EN1
EN1
GTREN2:bit15
EN47
RLT0 Output
RLT1 Output
RLT1 Output
Pin TRG0
External trigger 0
Pin TRG1
External trigger 1
Pin TRG11
External trigger 11
EN0 bit (GTREN0:bit0)
EN1 bit (GTREN0:bit1)
EN1 bit (GTREN0:bit1)
0
1
1
EN47 bit (GTREN2:bit15)
1
16bit Reload Timer 0
16bit Reload Timer 1
16bit Reload Timer 1
0
1
1
External trigger 0
0
External trigger 1
1
External trigger 11
1
GTRS0-GTRS23:bit14-8/bit6-bit0
TSEL0[6:0]/TSEL1[6:0]
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
A/D activation trigger
PPG output
PPG interrupt
Clock
GATE signal
Activation
trigger
MB91520 Series
MN705-00010-1v0-E
549