Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
37
4.16. General-purpose Trigger Setting Register : GTREN0 to
GTREN2
The bit configuration of the general-purpose trigger setting register is shown.
The general-purpose trigger setting register (GTREN) controls the generation of internal trigger to the PPG.
General-purpose trigger setting register 0 (GTREN0): Address 1A38
H
(Access:
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN15
EN14
EN13
EN12
EN11
EN10
EN9
EN8
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
General-purpose trigger setting register 1 (GTREN1): Address 1A3A
H
(Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN31
EN30
EN29
EN28
EN27
EN26
EN25
EN24
Initial value
0
0
0
0
0
0
0
0
Attribute
R0
R0
R0
R0
R0
R0
R0
R0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN23
EN22
EN21
EN20
EN19
EN18
EN17
EN16
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB91520 Series
MN705-00010-1v0-E
578