Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
General-purpose trigger setting register 2 (GTREN2): Address 1A3C
H
(Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
EN47
EN46
EN45
EN44
EN43
EN42
EN41
EN40
Initial value
0
0
0
0
0
0
0
0
Attribute
R0
R0
R0
R0
R0
R0
R0
R0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN39
EN38
EN37
EN36
EN35
EN34
EN33
EN32
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GTREN0, GTREN1, GTREN2 EN47 to EN0 Internal trigger input bits
EN47 to EN0
Explanation
0
Sets the level to "L".
1
Sets the level to "H".
These bits are used to generate a trigger at a specified internal trigger level.
If these bits are set to "0", a level "L" trigger is generated.
If these bits are set to "1", a level "H" trigger is generated.
Notes:
⋅
If an internal trigger (one of EN0 to EN47) is selected by the PPG activation trigger selection bits
(TSELii_[6:0]), the selected EN serves as the PPG trigger input bit.
⋅
When the state selected by the trigger input edge selection bits (PCN:EGS1, EGS0) is generated by
software with the use of the trigger input bit (selected one of EN0 to EN47), the trigger input bit services
as the PPG activation trigger.
MB91520 Series
MN705-00010-1v0-E
579