Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
26
4.3.1. Status Control Registers 0, 1 : BTxSTC (Base Timer
0/1 STatus Control)
The bit configuration of status control registers 0, 1 (BTxSTC) is shown below.
These registers control interrupt requests.
Notes:
⋅
Reserved bits must be set to "0".
⋅
For the read-modify-write instruction to TGIR, DTIR, and UDIR, "1" is read out.
⋅
These registers must be accessed in 8-bit mode.
⋅
These registers will also be initialized when reset mode is set
(writing of BTxTMCR:FMD = 000).
BTxSTC : Address Base_addr + 05
H
(Access: Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
TGIE
DTIE
UDIE
Reserved
TGIR
DTIR
UDIR
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0
R/W
R/W
R/W
R0,W0 R(RM1),W R(RM1),W R(RM1),W
[bit6] TGIE (TriGger Interrupt Enable) : Trigger interrupt request enable bit
This bit sets whether or not to generate a trigger interrupt request when a 16-bit PWM timer activation trigger
is detected (TGIR = 1).
[bit5] DTIE (DuTy Interrupt Enable) : Duty match interrupt request enable bit
This bit sets whether or not to generate a duty match interrupt request when the value of the 16-bit down
counter matches the value of the base timer x duty setting register (BTxPDUT) (DTIR = 1).
[bit4] UDIE (UnDerflow Interrupt Enable) : Underflow interrupt request enable bit
This bit sets whether or not to generate an underflow interrupt request when the down counter underflows
(UDIR = 1).
TGIE/DTIE/UDIE
Description
0
Disables.
1
Enables.
[bit2] TGIR (TriGger Interrupt Register) : Trigger interrupt request flag bit
This bit indicates that a 16-bit PWM timer activation trigger is detected. When this bit is "1" and the TGIE bit
is set to "1", a trigger interrupt request is generated.
[bit1] DTIR (DuTy Interrupt Register) : Duty match interrupt request flag bit
This bit indicates that the value of the 16-bit down counter matches the value of the duty setting register
(BTxPDUT) (a duty matches). When this bit is "1" and the DTIE bit is set to "1", a duty match interrupt
request is generated.
[bit0] UDIR (UnDerflow Interrupt Register) : Underflow interrupt request flag bit
This bit indicates that the 16-bit down counter value changed from "0000
H
" to "FFFF
H
" and an underflow
occurred. When this bit is "1" and the UDIE bit is set to "1", an underflow interrupt request is generated.
MB91520 Series
MN705-00010-1v0-E
659