Fujitsu FR81S User Manual
MB91520 Series
FUJITSU SEMICONDUCTOR LIMITED
FUJITSU SEMICONDUCTOR CONFIDENTIAL
vi
Access Unit and Address Position
Address
Block
+0
+1
+2
+3
000060
H
SSR0[R/W]
B, H, W
00001000
SIDR0[R]
B, H, W
SODR0[W]
B, H, W
XXXXXXXX
SCR0[R/W]
B, H, W
00000100
SMR0[R/W]
B, H, W
00000-0-
UART0
000064
H
UTIM0[R] H
(UTIMR0[W]H)
00000000 00000000
DRCL0[W]
B
XXXXXXX
UTIMC0[R/W]
B
0--00001
U-TIMER0
Although three types of access (Byte, Half-word, and Word access) are enabled, some registers have access
restrictions. For details, see "APPENDIX", or section "4. Detailed Register Description" of each chapter.
restrictions. For details, see "APPENDIX", or section "4. Detailed Register Description" of each chapter.
B, H, W : Byte access, Half-word access, and Word access are enabled.
B
: Byte access (Use the Byte access only.)
H
: Half-word access (Use the Half-word access only.)
W
: Word access (Use the Word access only.)
B, H
: Byte access and Half-word access only (The Word access is not allowed.)
H, W
: Half-word access and Word access only (The Byte access is not allowed.)
(Reference)
The following explains the address position during access.
The following explains the address position during access.
⋅
During Word access, the address is a multiple of 4 (the lowest order 2 bits are forcibly set to "00").
⋅
During Half-word access, the address is a multiple of 2 (the lowest order 1 bit is forcibly set to "0").
⋅
During Byte access, the address remains unchanged.
Therefore, if the SSR0 register is set to the Half-word access, for example, SSR0 + SIDR0 (SODR0) register at
address 060
address 060
H
is accessed.
(If the address offsets are +1 and +2 (for example, SIDR0+SCR0), the Half-word access is not allowed.)
Register name
Offset
Read only
Byte access, Half-word access, Word access
Write only
Initial Value
Readable/Writable
Address offset value/Register name
MN705-00010-1v0-E
(6)