Fujitsu FR81S User Manual

CHAPTER 20: RELOAD TIMER 

 

 

5. Operation 
 

FUJITSU SEMICONDUCTOR LIMITED 

CHAPTER : RELOAD TIMER 
FUJITSU SEMICONDUCTOR CONFIDENTIAL 

40 

Figure 5-11 Dual Reload Operation 

 

A

B

B

A

B

A

A

B

A:TMRLRA

B:TMRLRB

A

UF-A

UF-A

UF-A

UF-A

UF-B

UF-B

UF-B

Count from TMRLRA
Count from TMRLRB

A

A

A

B

B

B

A:TMRLRA

B:TMRLRB

TOUT

(When OUTL=0)

A

UF-A

UF-A

UF-A

UF-B

UF-B

Count from TMRLRA
Count from TMRLRB

Underflow

UF bit

CNTE(register)

CNTE(register)

TRG(register)

Data load

Waiting for activation trigger

Data load

Waiting for activation trigger

Waiting for effective gate input

TRG(register)

TTRG(pin)

TOUT

(When OUTL=0)

Timer reloaded

register

Underflow

UF bit

Timer reloaded

register

Dual Reload function (GATE=0 : trigger input)

Dual Reload function (GATE=1 : gate input, H input interval count)

TIN (pin) 

MN705-00010-1v0-E

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