Fujitsu FR81S User Manual
CHAPTER 20: RELOAD TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
41
5.3.5. Compare One-shot Operation
The compare one-shot operation is shown below.
When bit15, bit14:MOD[1:0] of the TMCSR register =10, and bit4:RELD of the TMCSR register =0, the
compare one-shot operation in which the counter value (TMR) and the value of TMRLRB register are
compared for each down count will be performed. After accepting a trigger, the value of the TMRLRA
register is loaded and the down count starts. When decrementing the count from the value of a compare
matched (TMR = TMRLRB), the TOUT output will be inverted. When an underflow occurs, count
operations stopped, TOUT output is initialized, and the timer go into the activation trigger wait state.
compare one-shot operation in which the counter value (TMR) and the value of TMRLRB register are
compared for each down count will be performed. After accepting a trigger, the value of the TMRLRA
register is loaded and the down count starts. When decrementing the count from the value of a compare
matched (TMR = TMRLRB), the TOUT output will be inverted. When an underflow occurs, count
operations stopped, TOUT output is initialized, and the timer go into the activation trigger wait state.
The value of TMRLRA indicates the time interval between the activation of a timer and the end of it and
the value of TMRLRB indicates the counter value when an output of the H width of TOUT output starts.
When OUTL="0" and TMR < TMRLRB, the TOUT output will become the "H level".
the value of TMRLRB indicates the counter value when an output of the H width of TOUT output starts.
When OUTL="0" and TMR < TMRLRB, the TOUT output will become the "H level".
Figure 5-12 TOUT Interval, Pulse Width
From the start of a down count to TMR = TMRLRB (while TMR is greater than or equal to TMRLRB), the
following operation will be performed.
following operation will be performed.
⋅ TOUT output continues to hold the initial value.
⋅ The timer continues to count.
⋅ If a down count from TMR = TMRLRB occurs, the following operation will be performed.
⋅ Inverts TOUT output.
⋅ The timer continues to count.
(For the compare operation in interval timer mode, bit7:EF bit of TMCSR register will not be set.)
⋅ If a down count from TMR = TMRLRB occurs, the following operation will be performed.
⋅ Inverts TOUT output.
⋅ The timer continues to count.
(For the compare operation in interval timer mode, bit7:EF bit of TMCSR register will not be set.)
If an underflow occurs, the following operation will be performed.
⋅ Sets bit2:UF bit of the TMCSR register.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.
⋅ Initializes TOUT output.
⋅ The timer stops with 0xFFFF.
⋅ Timer is waiting for an activation trigger.
The operation of the compare function changes depending on the setting relation between TMRLRA and
TMRLRB.
⋅ The timer stops with 0xFFFF.
⋅ Timer is waiting for an activation trigger.
The operation of the compare function changes depending on the setting relation between TMRLRA and
TMRLRB.
Trigger input
TOUT external pin output
↓
Cycle = TMRLRA
H width = TMRLRB
MB91520 Series
MN705-00010-1v0-E
768